The present invention relates to semiconductor memories, and particulary to static random access memories (SRAMs).
The sensing technique used in almost all the state-of-the-art static RAMs is analog amplification of the differential signal on the bit-lines. The storage cell when accessed through two pass devices puts a differential voltage on the bit-lines. FIG. 1 shows two of the conventional load device schemes. It is desirable to have bit lines precharged to a certain voltage level and then sense the differential signal available on the bit lines during read mode. Furthermore, the differential signal on the bit lines is designed to be as small as possible without degrading the read performance, in order not to disturb unselected memory locations during the read operation. As the signal gets smaller, the sensing/amplification becomes more difficult as well as slower, but, the bit-lines recover much faster from the differential voltage which they may have received during the previous cycle.
As FIG. 1A shows, a conventional state-of-the-art fully static RAM uses load devices to keep the bit-lines pre-charged as well as to maintain an optimum signal swing on the bit-lines during Read mode. Writing into an accessed cell is performed by phoms on the bit-lines a very large signal (from the data input drivers). Thus it is also important to keep the signal swing during read mode much smaller than the signal during Write mode, in order to avoid any alterations of data during read mode. The load devices M1 and M2 as shown in FIG. 1A have a constant voltage VGG on their gate terminals. The gate bias voltage is chosen in accordance with the storage cell characteristics and other AC and DC design parameters, such as sense amplifier gain etc. The bit-lines are usually precharged to a high voltage level. This volltage level depends on the gate bias of the load voltage devices for the bit-lines.
An alternate scheme (FIG. 1B) is to use a depletion type devices in the load configuration, i.e., to tie the gate terminal of the depletion device to the bit-line which is also the source terminal of the depletion device. In either configuration, during Read mode, the load current either increases or at best remains constant as the bit-line voltage is lowered from the precharged level. The cell being accessed has to overcome the constant current or increasing current in order to provide sufficiently large signal on the bit-lines. The load current from depletion load devices may not remain constant either and actually may increase depending upon the backgate biaseffects. Thus, the conventional state-of-the-art sense amplifiers have a built-in conflict between the storage cell devices and the bit-line load devices. This conflict results in lower driver speed and higher power dissipation.
This conflict has even worse effects on power dissipation during the Write mode since a larger signal is being forced onto the bit-lines. During read operation the cross-coupled devices of the static memory cell become the driver devices for the bit-lines, while the series combination of the bit-line load devices and the cell pass devices act as the load device for the cell inverter. If the gate of the bit line load devices are at a constant voltage, the current through them will increase as the cell driver device tries to pull the corresponding bit-line low during read mode. During write operation the bit-line pull-up devices alone act as load devices while the data-write devices (M3,M4) act as drive devices. This configuration needs very high gain in order to generate a large differential voltage on the bit lines required during a write operation.
The present invention improves the pre-sense amplifier by using positive feedback from the sense amplifier to the bit-line pull-up (load) devices. The bit-lines each have a depletion-mode transistor as a load device, as in conventional sense amplifiers, but the gate of each of the load device is NOT connected to the corresponding bit-lines which are the source terminals of these depletion load devices. The gate terminals of the load devices are instead connected to the outputs of the pre-sense amplifier. The inputs to the pre-sense amplifier are the bit-lines, as in the conventional circuits. The pre-sense amplifier is a simple differential source-follower amplifier with nearly unity gain. The bit-lines are precharged to VDD by current through the depletion load devices. The pre-sense amplifier provides a voltage shift to the bit-line differential voltage. The bit-lines have a dc offset of approximately VDD. The output differential signal of the pre-sense amplifier stage is offset by about (1/2) VDD. Also, the depletion device Vt is approximately (1/2) VDD. These voltage conditions imply a near cut-off (and therefore high-gain) operation of the depletion feed-back load devices. The pre-sense-amplifier stage is powered up by a column select line which provides a current path to ground via the depletion constant current source. When a cell is being read, the initial bit-lines differential voltage gets a downward voltage shift from the pre-sense amplifier. This differential voltage appears on the gates of the load devices, whose transconductance is therefore modified such that the bit-line going low sees a higher impedance depletion load (feed-back) device, whereas the other bit line sees a lower impedance. This positive feedback helps the bit-lines develop an even larger signal. The cell node storing a high voltage gets restored by the corresponding bit-line, since it stays at VDD level, and the cell node storing a low level does not get pulled too high, since the driver device is held in ON state by the opposite node storing a high. This approach is particularly desirable for high impedance load memory cells, such as the poly resistor load cell or the sub-threshold load cell. This circuit approach actually refreshes the memory cell information, which may have decayed due to excessive leakage or alpha particle incidence. The high impedance load cells are more prone to these types of leakage mechanism.
The advantages to be obtained by improving the sensing operation are interrelated. That is, any advantage in the sensing operation, such as, is provided by the present invention, can be used to provide either a memory having a faster access time or a memory having lower power dissipation, or both. For example, if it is possible to configure the memory bit line loads and sense amplifiers so that the cell drivers are required to pass on smaller current (or a smaller average current) during each read cycle, the cell layout can be revised to used narrower drivers (if they are not already minimum-width, or other process in parameters perinthages with oxide thickness) may be eased.
It is an object of the invention to provide a static random access memory wherein the total charge transferred by the driver transistors of an access memory cell during a read operation is reduced.
It is a further object of the present invention to provide a static random access memory wherein the total charge which is required to be transferred by the write transistors drawing a write operation is reduced.
Thus it an object of the present invention to provide a static random access memory which avoids read-after-read errors.
It is a further object of the present invention to provide a static random access memory (SRAM) having a short write time.
It is a further object of the present invention to provide a SRAM wherein the cell loads are high-impedance, and which has short access time.
It is a further object of the present invention to provide a SRAM having low power dissipation and rapid access.
It is a further object of the present invention to provide a SRAM wherein the bit line loads do not present a low impedance to the write signal during the write operation.
It is a further object of the present invention to provide a SRAM wherein the SRAM cell is required to provide only a small differential signal during the read operation.
It is a further object of the present invention to provide a SRAM wherein each memory cell being read is required to sink a reduced average current during the read out operation.
It is a further object of the present invention to provide a static random access memory wherein any degradation of the signal stored in memory cell is restored immediately when that cell is read.
Many of the problems discussed above can be avoided by using a precharge cycle prior to every read cycle. This technology is discussed, for example, in the 1982 ISSCC paper entitled "A NMOS 64K static RAM," which is hereby incorporated by reference.
However, this technology requires substantially more complex peripheral circuits. In effect, it is not really a static RAM any more, but is what has been referred to as a pseudo-static RAM. That is, many of the overhead requirement of dynamic RAM technology are thus incurred, without correspondently inheriting the advantages of dynamic RAM technology.
Thus it is an object of the present invention to provide a random access memory which does not require precharge on every read cycle.
It is the further object of the present invention to provide a random access memory that does not require any peripheral circuits for the bit line precharging.
According to the present invention there is provided:
An array of memory cells, each memory cell being selectively accessible to provide a differential current signal at a pair of output nodes thereof;
A plurality of bit lines, said bit lines being selectively connected in pairs to said respective pairs of output nodes of a plurality of said cells;
A plurality of bit line loads, one pair of said bit line loads being connected to each pair of said bit lines, the impedance of said bit line loads being dynamically varied in accordance with the differential current signal applied to said respective corresponding pair of bit lines by a respective one of said cells which has been selected.